Display device

ABSTRACT

The display device ( 6 ) comprise s a display ( 2 ) and generating mean s ( 10, 8 ). The display ( 2 ) has a plurality of light emitting elements ( 3 ), and data lines ( 13 ) for providing pulse width modulation (PWM) signals to the light emitting elements ( 3 ). The generating means ( 10, 8 ) are coupled to the data lines ( 13 ) for generating, during time intervals (SF) of a frame period, at least a first non-zero emission level (L(V 1 ;C 1 ;I 1 )) of a light emitting element ( 3 ) during a first one of the time intervals (SF) and a second non-zero emission level (L(V 2 ; C 2; 12 )) during a second one of the time intervals (SF).

The invention relates to a display device comprising a display with aplurality of light emitting elements. The invention also relates to anelectric device comprising such a display device and to a method ofdriving a display.

Display devices employing light emitting elements or pixels on or over asubstrate are becoming increasingly popular. These light emittingelements may be light emitting diodes (LEDs) incorporated in or formingdisplay pixels that are arranged in a matrix of rows and columns. Thematerials employed in such LEDs are suitable to generate light if acurrent is conveyed through these materials, such as in particularpolymeric (PLED) or organic (OLED) materials. Accordingly the LEDs haveto be arranged such that a current can be driven through these lightemitting materials. Typically, passively and actively driven matrixdisplays are distinguished. For active matrix displays, the displaypixels themselves comprise active circuitry such as one or moretransistors.

In active matrix displays the variation of the parameters of thetransistors is an important issue for e.g. the uniformity of thedisplay. By operating the transistors at a reasonably high current thelight emission of the LEDs is less sensitive to variations in thethreshold voltage of the transistors, the variation of which has beenrecognized as a major cause of non-uniformity of the display. If the LEDoperates with only a few levels of brightness, each of themcorresponding to a specific level of current, such an operating schemeis called digital driving.

Since by digital driving only a few levels of brightness are available,as is well known, more gray levels may be made by using pulse widthmodulation (PWM). For example, the light emitting elements of thedisplay may be either turned “on” or “off” during any of a number ofsubfields in a frame period, in dependence on a desired gray level. Thesubfields are time intervals within a frame period.

However, when applying row at a time addressing for large displayscomprising a high number of selection lines associated with rows oflight emitting elements, the available addressing time for addressing orselecting one row may be in the order of sub-microseconds. In order todeal with these very short addressing times a multiline addressing (MLA)scheme is preferable. The MLA scheme is sometimes also referred to as acombined line or row addressing approach. In an MLA scheme dead timesbetween the subfields are minimized by proper algorithms. Such anapproach is e.g. disclosed in EP application no. 01204541.5. In thepresent text MLA is considered to be a species of PWM addressing, i.e.PWM includes MLA.

A problem of PWM techniques is that they do not provide an optimal rangeof gray scale levels for a display.

It is an object of the invention to significantly enhance the number ofgray scale levels of PWM addressed displays.

This object is achieved by providing a display device comprising:

a display with a plurality of light emitting elements, and data linesfor providing pulse width modulation (PWM) signals to the light emittingelements; and

means coupled to the data lines for generating, during time intervals ofa frame period at least a first non-zero emission level of a lightemitting element during a first one of the time intervals and a secondnon-zero emission level during a second one of the time intervals.

Next to the first and second non-zero level, a zero level and additionalnon-zero levels may be present.

Rather than increasing the time interval when a subfield with a largerweight is required, a second emission level higher than the firstemission level should be employed that allows to generate a subfield ofa larger weight to be generated without increasing the time interval.

As the duration of a subfield is shortened in this way, more subfieldsmay be generated during a frame period, resulting in an enhanced numberof gray scale levels for the display. The generating means may comprisea data driver and a control unit for receiving information about animage to be displayed and for determining drive signals and timingsignals for driving the data driver. The display is preferably an activematrix display. Such a display allows a part of the plurality of lightemitting elements to emit light, while another part is being addressedor erased. This is made possible because each of the light emittingelements includes an active element, such as a thin film transistor incombination with a memory element, for example, a capacitor. The matrixdisplay may be an organic LED or a polymeric LED display.

In an embodiment a multiline addressing scheme is applied, which resultsin a further reduction of dead time within a frame period, therebyallowing for more time intervals for generating light, and henceenabling more gray levels to be generated.

The generating means may also comprise a row selection circuit forselecting a part of the plurality of light emitting elements.

Preferably the time intervals of the PWM addressing scheme have a binaryweighted duration. These time intervals may be arranged in mixed uporder with respect to their duration, i.e. time intervals of long andshort duration may be adjacent to each other in order to achieve anoptimal use of the frame period. Preferably, each of the emission levelsis associated with a set of time intervals having a binary weightedduration.

In an embodiment of the invention the emission levels of the lightemitting elements are provided via the data lines. Preferably, this isdone in a sequential mode wherein during a frame period first all timeintervals are processed sequentially for the first emission level andsubsequently for the second emission level etc. This driving scheme issuitable for both voltage programmed and current programmed lightemitting elements.

In the intermixed mode, time intervals associated with the emissionlevels may be distributed within the frame period as desired, forexample, the first emission level and the second emission level areemployed alternately for each time interval. This driving scheme issuitable for both voltage programmed and current programmed lightemitting elements. For current programmed light emitting elements it ispreferred in this embodiment to employ several independent currentsources, since the emission level of the light emitting element maychange frequently within a frame period. In such a case a single currentsource is less suitable, since current sources are generally not able toswitch sufficiently precisely between various current magnitudes withina short time.

For current programmable light emitting elements it may be advantageousto bring the data line at a suitable voltage level before applying thecurrent in order to overcome delays due to parasitic capacitances in thedata lines.

The driving scheme using a power line to couple a first or a secondsupply voltage to the light emitting elements is particularly suitablefor voltage programmed light emitting elements.

The invention further relates to an electric device comprising a displaydevice as described in the previous paragraphs. Such an electric devicemay relate to handheld devices such as a mobile phone, a PersonalDigital Assistant (PDA) or a portable computer as well as to devicessuch as a Personal Computer, a computer monitor, a television set or adisplay on e.g. a dashboard of a car.

The invention will be further illustrated with reference to the attacheddrawings, which show preferred embodiments according to the invention.It will be understood that the device and method according to theinvention are not in any way restricted to these specific and preferredembodiments. In the drawings:

FIG. 1 shows an electric device comprising a display according to anembodiment of the invention;

FIG. 2 shows a display device for an active matrix display according toan embodiment of the invention;

FIG. 3 shows a schematical timing diagram representing pulse widthmodulation (PWM) according to the prior art;

FIG. 4 shows a schematical timing diagram representing pulse widthmodulation employing an MLA scheme according to the prior art;

FIG. 5 shows a first embodiment of the invention in a voltage programmedpixel circuit employing multilevel power addressing (MPA) in theintermixed mode;

FIG. 6 shows a schematical timing diagram representing pulse widthmodulation employing multilevel power addressing (MPA) for theembodiment shown in FIG. 5;

FIG. 7 shows a conceptual timing diagram of a second embodiment of theinvention, employing multilevel power addressing (MPA) in the sequentialmode;

FIG. 8 shows a third embodiment of the invention in a voltage programmedpixel circuit, employing multilevel column addressing (MCA) in theintermixed mode;

FIG. 9 shows a schematical timing diagram representing pulse widthmodulation employing multilevel column addressing (MCA) for theembodiment shown in FIG. 8;

FIG. 10 shows a fourth embodiment of the invention in a currentprogrammed pixel circuit; and

FIG. 11 shows a fifth embodiment of the invention in a modified currentprogrammed pixel circuit. The same reference numbers in different FIGS.refer to the same elements.

FIG. 1 shows an electric device 1 comprising a display 2 having aplurality of light emitting elements or display pixels 3 arranged in amatrix of rows 4 and columns 5.

FIG. 2 shows a schematic illustration of a display device 6, comprisingthe display 2 of the electric device 1 as shown in FIG. 1. The display 2comprises a row selection circuit 7 and a data driver 8. Information ordata, such as (video) images, received via line 9 and to be presented onthe display 2 is input to the control unit 10, which information or datais subsequently transmitted by the control unit 10 to the appropriateparts of the data driver 8 via line 11. The selection of the rows 4 ofthe display pixels 3 is performed by the row selection circuit 7 viaselection lines 12. Data are written to the display pixels 3 from thedata driver 8 via data lines 13.

Moreover the control unit 10 controls the power supply of the displaypixels 3 via power lines 14.

FIG. 3 displays a timing diagram illustrative of pulse width modulation(PWM for forming gray scale levels in display technologies. In FIG. 3only eight rows 4 of the display 2 are shown in the vertical direction,while in the horizontal direction the state of each row as a function oftime t is shown. Only a fraction of a frame period is shown. The frameperiod is divided into subfields or time intervals SF of differentduration in accordance with the number of gray scale levels to bedisplayed. FIG. 3 only shows two time intervals or subfields, indicatedby SF1 and SF2, of the frame period for the eight rows 4. In the timeintervals SF several states can be distinguished for the display pixels3, viz, addressing (hatched blocks), burning (black blocks), erasing(dotted blocks) and dead time (white blocks). If the time intervals SFof the frame period have a binary weighted distribution, the timeintervals represent a bit representation of the number of gray scalelevels. E.g. if the frame period is divided into 6 binary weighted timeintervals SF1 . . . 6, SF1 represents gray scale bit level 1, SF2 grayscale bit level 2, SF3 4, SF4 8, SF5 16 and SF6 32, which results in2⁶=64 possible gray scale levels (=6-bit) in total.

For a display 2 comprising 480 rows 4, a frame time of 20 ms, with 64gray scale levels results in an available time interval of 0.65microseconds for subfield SF1.

FIG. 4 displays a timing diagram employing multiline row addressing(MLA) in combination with PWM. As can be clearly observed, in MLA theamount of dead times between the time intervals SF and for the rows 4 isvariable and can be minimized by applying proper algorithms. As a resultthe available time in the frame period is used more efficiently. It isnoted that it may be preferred to shuffle or mix up the time intervalswithin the frame period in order to obtain the most efficient result.This means that in the example of the previous paragraph the sequence oftime intervals is not necessarily SF1, SF2, SF3, SF4, SF5, SFA6, bute.g. SF3, SF1, SF6, SF4, SF2, SF5.

FIG. 5 shows a first embodiment of the invention in a voltage programmedpixel circuit 15. Only a single display pixel 3 of the display 2 isshown, comprising transistors T1 (drawn as a switch) and T2, a capacitorC and a LED. Display pixel 3 can be selected via selection line 12 andprovided with data via data line 13. The display pixel 3 is powered viapower line 14. The selection signals provided over the selection line 12are represented in the right-hand diagram, wherein the on state referssequentially to addressing AD and erasing ER. The data provided over thedata line 13 is a voltage that is able to either fully open or fullyclose the transistor T2, represented by “off” and “on” in the right-handdiagram, i.e. T2 behaves as a switch and the light emission level of theLED is dependent on the supplied voltage over the power line 14.Different voltages give rise to different emission levels of the LED.This effect is used to enhance the number of gray scale levels within aframe time. In FIG. 5 PWM-signals are supplied to the display pixel 3via selection line 12, during the first time interval SF1 the displaypixel 3 being brought first in a first emission state (corresponding tothe first emission level), indicated by V1, and in a subsequent timeinterval SF1 of the same duration in a second emission state(corresponding to the second emission level), indicated by V2. This isshown in the right-hand diagram. These events can be repeated (notshown) in the next time interval SF2, wherein burning is subsequentlyperformed at V1 and V2 again within the time interval SF2. If n powerlevels are available over power line 14, i.e. multilevel poweraddressing (MPA), the sequence for N time intervals SF in one frameperiod may be e.g. SF1(V1), SF1(V2), SF1(V3) . . . SF1(Vn); SF2(V1) . .. SF2(Vn); . . . ; SFN(V1) . . . SFN(Vn). This is an example of theintermixed mode, wherein the emission state of the LED is variedrepeatedly.

In the MPA-approach the individual time intervals SF are in fact used ntimes instead of only once. As a result the number of bits for grayscale levels is best enhanced by a factor of n. FIG. 6 displays a timingdiagram for a display 2 of eight rows 4, wherein during SF1 first afirst emission state V1 (light gray blocks) is employed for the displaypixels 3, followed by a second emission state V2 (black blocks) during asubsequent identical time interval SF1.

In FIG. 7 a conceptual timing diagram employing MPA in a sequential modeis displayed for a 16 gray scale level (=4 bit) PWM addressing scheme ina single row 4. In the sequential mode, first all time intervals SF fora first emission state V1 are supplied over the selection line 12followed by all time intervals SF for a second emission state V2. It isnoted once more that the time intervals SF are not necessarily orderedaccording to the time duration but may be mixed up if this provides formore efficient usage of the frame period. In FIG. 7 the numbers indicatethe number of gray scale levels associated with the time intervals SF1 .. . SF4. The second emission state V2 is chosen such that the lightemission level L(V2) of the display pixel 3 in the second emission stateV2 is equal to the number of gray scale levels in the frame period, i.e.16, times the light emission level L(V1) of the light emitting elementsin the first emission state. In the upper timing diagram MPA is employedin the sequential mode. In order to achieve e.g. gray scale level 100,it is sufficient to provide the hatched bits over the selection line 12to the display pixel 3 in a frame period. The maximum number of graylevels is 256 in one frame period. For the sake of comparison the lowertiming diagram displays the situation without MPA. In this case the sameamount of time allows only 32 gray scale levels in one frame period.More generally, if n power levels are available over power line 14, i.e.multilevel power addressing (MPA), the sequence for N time intervals inone frame period for the sequential mode is SF1(V1), SF2(V1), SF3(V1) .. . SFN(V1); SF(V2) . . . SFN(V2); . . . ; SF1(Vn) . . . SFN(Vn).

FIG. 8 shows a third embodiment of the invention in a voltage programmedpixel circuit 15, employing multilevel column addressing (MCA) in theintermixed mode. Selection signals are again applied over the selectionline 12 as shown in the right-hand diagram. In this embodiment changingthe column voltage over the data lines 13, shown in the right-handdiagram, creates the additional gray scale levels. The power level,supplied over the power line 14, for the display pixels 3 is keptconstant. It is noted however that MPA and MCA can be employed both inone addressing scheme. In this embodiment a semi-digital approach istaken, wherein a limited amount of voltage levels can be applied to thegate of transistor T2 including the voltage level for switching off T2.T2 thus no longer just functions as a switch, as was the case in FIG. 5,but is a semi-analog component such that the LED is current driven atdata level C1, whilst it may still act as a switch at data level C2. Itis noted that this state is beneficial from the perspective ofdegradation of the LED, since with the currently used polymer materialsthe lifetime of voltage driven LEDs is shorter.

The light emission states of the LED are determined by the number ofvoltages that are applied to the gate of T2 over data lines 13. As inFIG. 5, in FIG. 8 a preferred embodiment doubles the number of grayscale levels by providing over the data line 13 a first emission stateassociated with C1 and a second emission state associated with C2 forthe display pixel 3 for each time interval SF. The levels C1 and C2 arepreferably chosen such that the light emission level L(C2) of the LED atstate C2 equals the number of gray scale levels times the light emissionlevel L(C1) at state C1. If e.g. the PWM is 4 bits (16 gray scalelevels), applying multilevel column addressing (MCA) yields 256 grayscale levels. In general if n voltage levels are available over the datalines 13, i.e. multilevel column addressing (MCA), the sequence for Ntime intervals in one frame period may be e.g. SF1(C1), SF1(C2), SF1(C3). . . SF1(Cn); SF2(C1) . . . SF2(Cn); . . . ; SFN(CL) . . . SFN(Cn) forthe intermixed mode. FIG. 9 shows the timing diagram employing aPWM-MLA-MCA addressing scheme. The light gray blocks represent the firstemission state C1, while the black blocks represent the second emissionstate C2.

Like FIG. 5, FIG. 8 can also be employed in a sequential mode, resultingin a general case in the sequence SF1(C1), SF2(C1), SF3(C1) . . .SFN(C1); SF1(C2) . . . SFN(C2); . . . SF1(Cn) . . . SFN(Cn).

Multiple column addressing (CA) schemes can also be employed in currentprogrammable pixel circuits. FIG. 10 shows a known current programmedpixel circuit 16 having a switched current mirror circuit. The currentmirror may also be operated using other types of current mirrorcircuits. The data line 13 can be used to provide n current levels I₁ .. . I_(n) to activate the LED to n different emission states in theframe period. The zero level can either be a voltage level, which ispreferred for higher speeds, or a current level to deactivate the LEDduring addressing or erasing. During addressing or erasing the switchtransistors T0 and T3 are on, switch transistor T4 is off and drivingtransistor T11 is programmed to drive the current I_(i). In the burningperiod, T0 and T3 are switched off, T4 is turned on and T11 delivers thecurrent I_(i) to the LED.

In a preferred embodiment n=2, i.e. a current I₁ is associated with afirst emission state and a current I₂ is associated with a secondemission state of the display pixel. Current I₂ is preferably such thatthe light emission level L(I₂) in the second emission state equals thelight emission level L(I₁) in the first emission state times the numberof gray scale levels for the first emission state. A circuit accordingto FIG. 10 preferably is operated in the sequential mode, therebyyielding the sequence SF1(I₁), SF2(I₁), SF3(I₁) . . . SFN(I₁); SF1(I₂) .. . SFN(I₂); . . . ; SF1(I_(n)) . . . SFN(I_(n)). The embodiment shownin FIG. 10 is less suitable for the intermixed mode since the currentsource is normally not capable of switching quickly between precisecurrent levels.

To enable the intermixed mode in employing MCA schemes for currentprogrammable pixel circuits it is preferred to use several independentcurrent sources providing a suitable current magnitude over the dataline 13. In FIG. 11 such a modified current programmable pixel circuit17 is shown, having two independent current sources providing currentsI1 and I2 over the data lines 13. Switch transistors S1 and S2,controlled by the control unit 10 over lines 18, are adapted to supplycurrent I1 and I2, respectively, in the appropriate time interval SF.The other current may be dumped in a dumping unit 19. For a 4-bit PWMaddressing scheme in the intermixed mode the scheme may read SF3(I1),SF3(I2), SF2(I1), SF2(I2), SF4(I1), SF4(I2), SF1(I1), SF1(I2). Note thatin this sequence the time intervals are mixed up with respect to theirduration, which may be preferred for efficient usage of the frameperiod.

Current programmable pixel circuits 16, 17 are known to suffer fromtiming problems due to parasitic coupling. When a current pulse iswritten to a display pixel 3, the parasitic capacitance of the datalines 13 corresponding to the column 5 of display pixels 3 is to becharged first. This capacitance may be of a significantly high level andis dependent on the size of the display 2. The current programmablepixels circuits 16, 17 shown in FIGS. 10 and 11 may therefore be suitedfor pre-charging the data lines 13, i.e. bringing the data lines 13 to asuitable voltage before supplying the current. This pre-charging can bemanaged by the data driver 8 via the control unit 10.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.Use of the verb “comprise” and its conjugations does not exclude thepresence of elements or steps other than those stated in a claim. Thearticle “a” or “an” preceding an element does not exclude the presenceof a plurality of such elements. The invention may be implemented bymeans of hardware comprising several distinct elements, and by means ofa suitably programmed computer. In the device claim enumerating severalmeans, a number of these means may be embodied by one and the same itemof hardware. The mere fact that certain measures are recited in mutuallydifferent dependent claims does not indicate that a combination of thesemeasures cannot be used to advantage.

1. Display device (6) comprising: a display (2) with a plurality oflight emitting elements (3), and data lines (13) for providing pulsewidth modulation (PWM) signals to the light emitting elements (3); andmeans (10, 8) coupled to the data lines (13) for generating, during timeintervals (SF) of a frame period, at least a first non-zero emissionlevel (L(V1; C1; I1)) of a light emitting element (3) during a first oneof the time intervals (SF) and a second non-zero emission level (L(V2;C2; 12)) during a second one of the time intervals (SF).
 2. Displaydevice (6) according to claim 1, wherein the display (2) furthercomprises selection lines (12), each selection line (12) being coupledto a part of the plurality of light emitting elements (3), thegenerating means (10, 8) being further coupled to the selection lines(12) for applying a multiline addressing scheme to the data lines (13)and the selection lines (12).
 3. Display device (6) according to claim1, wherein the generating means (10, 8) are adapted to generate timeintervals (SF) of a substantially binary weighted duration in any order.4. Display device (6) according to claim 1, wherein the generating means(10, 8) are adapted to generate the first (L(V1; C1; I1)) and secondemission level (L(V2; C2; I2)) via the data lines (13) in a sequentialmode.
 5. Display device (6) according to claim 1, wherein the generatingmeans (10, 8) are adapted to generate the first (L(V1; C1; I1)) andsecond emission level (L(V2; C2; I2)) via the data lines (13) in anintermixed mode.
 6. Display device (6) according to claim 3, wherein thegenerating means (10, 8) comprise a control unit (10), and a data driver(8) comprising a first current source (I1) for generating the firstemission level (L(I1)) and a second current source (I2) for generatingthe second emission level (L(I2)).
 7. Display device (6) according toclaim 5, wherein the generating means (10, 8) are adapted to pre-chargethe data lines (13) before coupling one of the current sources (I1, I2)to one of the data lines (13).
 8. Display device (6) according to claim1, further comprising a power line (14) for coupling a first supplyvoltage (V1) to the plurality of light emitting elements (3) forgenerating the first emission level (L(V1)) and a second supply voltage(V2) for generating the second emission level (L(2)), respectively. 9.Display device (6) according to claim 1, wherein the generating means(10, 8) are adapted to generate the second emission level (L(V2; C2;I2)) at a level substantially equal to the first emission level (L(V1;C1; I1)) multiplied by a number of selectable combinations of timeintervals (SF).
 10. Electric device (1) comprising a display device (6)according to claim
 1. 11. Method for driving a display device (6)comprising a display (2) with a plurality of light emitting elements (3)and data lines (13) coupled to the light emitting elements (3), themethod comprising the steps of: providing pulse width modulation (PWM)signals to the data lines (13); and generating in synchronization withthe pulse width modulation (PWM) signals, during time intervals (SF) ofa frame period, at least a first non-zero emission level (L(V1; C1; I1))of a light emitting element (3) during a first one of the time intervals(SF) and a second non-zero emission level (L(V2; C2; I2)) during asecond one of the time intervals (SF).